June 18, 2006


Breakfast (8:00 to 8:25)



Welcome (8:25 to 8:30)

Organizers:  Lieven Eeckhout, Ghent University

                     Joshua J. Yi, Freescale Semiconductor


Session 1: Statistics (8:30 to 10:30)

Chair: Resit Sendag, University of Rhode Island


Statistically Rigorous Regression Modeling for the Microprocessor Design Space

Benjamin C. Lee, Harvard University

David M. Brooks, Harvard University


STATSHARE: A Statistical Model for Management Sharing via Decay

Pavlos Petoumenos, University of Patras

Georgios Keramidas, University of Patras

Hakan Zeffer, Uppsala University

Stefanos Kaxiras, University of Patras

Erik Hagersten, Uppsala University


Exploring the Impact of Normality and Significance Tests in Architecture Experiments

Pitchaya Sitthi-amorn, University of Virginia

Dee A. B. Weikle, University of Virginia

Kevin Skadron, University of Virginia


Measuring the Cost of a Cache Miss

Thomas R. Puzak, IBM TJ Watson

Alan Hartstein, IBM TJ Watson

Philip E. Emma, IBM TJ Watson

Vijayalakshmi Srinivasan, IBM TJ Watson



Break (10:30 to 11:00)



Session 2: Workload characterization (11:00 to 12:00)

Chair: Kevin Skadron, University of Virginia


Sim-SODA: A Unified Framework for Architectural Level Software Reliability Analysis

Xin Fu, University of Florida

Tao Li, University of Florida

Jose Fortes, University of Florida


Stallscope: Illuminating the Black Box

Leick Robinson, Freescale Semiconductor



Lunch (12:00 to 1:30)



Session 3: Simulation (1:30 to 3:00)

Chair: Joshua J. Yi, Freescale Semiconductor


Hardware-Agnostic Full-System Power Modeling

Dimitris Economou, Stanford University

Suzanne Rivoire, Stanford University

Christos Kozyrakis, Stanford University

Partha Ranganathan, Hewlett-Packard Labs


A Novel Evaluation Methodology to Obtain Fair Measurements in Multithreaded Architectures

Javier Vera, BSC

Francisco J. Cazorla, BSC

Alex Pajuelo, UPC

Oliverio J. Santana, University of Las Palmas

Enrique Fernandez, University of Las Palmas

Mateo Valero, BSC and UPC


FastMP: A Multi-core Simulation Methodology

Shobhit Kanaujia, Intel

Irma Esmer Papazian, Intel

Jeff Chamberlain, Intel

Jeff Baxter, Intel


Break (3:00 to 3:30)



Panel: “Multi-Core Simulation Methodology” (3:30 to 5:30)


Lieven Eeckhout, Ghent University



Krste Asanovic, MIT

David August, Princeton University

Doug Burger, University of Texas at Austin

Joel Emer, Intel

Babak Falsafi, Carnegie Mellon University

David Wood, University of Wisconsin – Madison


Panel theme:

Next generation microprocessor chips will feature tens or even hundreds of processing cores on a single die. Current design methodologies that rely on detailed cycle-by-cycle simulation are unlikely to be viable in the near future; simulation time will explode by adding additional cores on the chip. The goal of this panel is to discuss these issues and to present potential solutions for this major challenge.



Closing Remarks (5:30 to 5:35)

Organizers:  Lieven Eeckhout, Ghent University

                     Joshua J. Yi, Freescale Semiconductor