June 21, 2009



Welcome (8:25am to 8:30am)

Organizers:     Lieven Eeckhout (Ghent University)

                        Thomas Wenisch (University of Michigan)

                        Joshua J. Yi (Freescale Semiconductor)



Keynote (8:30am to 9:20am)

Title:    Modeling challenges for the exascale era

            Partha Ranganathan (Hewlett Packard Labs)


Abstract: With the recent beginning of the era of petascale computing (1015 flops), the next grand challenge is to design systems and datacenters for the exascale era (1018 flops). In addition to the orders of magnitude increases in performance, system designs in the exascale era will be constrained by significant challenges in power consumption, heat dissipation, manageability, scalability, and reliability. In addition, new and different markets like cloud computing and emerging economies potentially motivate different design considerations. All these trends motivate a corresponding rethinking of modeling and benchmarking approaches. In this talk, I will discuss the needs and opportunities for future modeling approaches to address the challenges for systems designs for the exascale era.


Biography: Partha Ranganathan is currently a distinguished technologist at Hewlett Packard Labs. His research interests are in systems architecture and management, power management and energy-efficiency, and systems modeling and evaluation. He is currently the principal investigator for the exascale datacenter project at HP Labs that seeks to design next-generation servers and datacenters and their management. He was a primary developer of the publicly distributed Rice Simulator for ILP Multiprocessors (RSIM). Partha received his B.Tech degree from the Indian Institute of Technology, Madras and his M.S. and Ph.D. from Rice University, Houston. Partha's work has been featured in various venues including the Wall Street Journal, Business Week, San Francisco Chronicle, Times of India, slashdot, youtube, and Tom's hardware guide. Partha has been named one of the world's top young innovators by MIT Technology Review, and is a recipient of Rice University's Outstanding Young Engineering Alumni award.



Session 1: Modeling (9:20am to 10:00am)

Chair: Thomas Wenisch (University of Michigan)


A Hybrid Analytical DRAM Performance Model

George L. Yuan and Tor M. Aamodt (University of British Columbia)


Navigo: An Early-Stage Model to Study Power-Constrained Architectures and Specialization

Mark Hempstead, Gu-Yeon Wei, and David Brooks (Harvard University)



Morning Break (10:00am to 10:30am)



Session 2: Measurement and Methodology (10:30am to 12:10pm)

Chair: Lieven Eeckhout (Ghent University)


CMP Memory Modeling: How Much Does Accuracy Matter?

Sadagopan Srinivasan (Intel), Li Zhao (Intel), Brinda Ganesh (Intel), Bruce Jacob (University of Maryland), Mike Espig (Intel), and Ravi Iyer (Intel)


Measuring and Modeling Variability using Low-Cost FPGAs

Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, and Jose Renau (University of California, Santa Cruz)


FIESTA: A Sample-Balanced Multi-Program Workload Methodology

Andrew Hilton, Neeraj Eswaran, and Amir Roth (University of Pennsylvania)


Virtual-GEMS: An Infrastructure to Simulate Virtual Machines

Antonio García-Guirado, Ricardo Fernández-Pascual, and José M. García (Universidad de Murcia)


PARSEC 2.0: A New Benchmark Suite for Chip-Multiprocessors

Christian Bienia and Kai Li (Princeton University)



Closing Remarks (12:10pm to 12:15pm)

Organizers:     Lieven Eeckhout (Ghent University)

                        Thomas Wenisch (University of Michigan)

                        Joshua J. Yi (Freescale Semiconductor)



Reception (6:00pm)