June 22, 2008



Welcome (1:00pm to 1:05pm)

Organizers:     Lieven Eeckhout (Ghent University)

                        Joshua J. Yi (Freescale Semiconductor)



Keynote (1:05pm to 2:00pm)

Title: How Many Simulators Does it Take to Build a Correct Chip? [Slides]

            Steve Keckler (University of Texas at Austin)


Abstract: While this question sounds like start of a bad joke, the answer is a lot more than you might expect. In this talk, I will describe our experience in the design and implementation of the TRIPS system prototype, which includes a custom chip with a data-driven instruction set architecture and a scalable, distributed microarchitecture. In particular, I will provide an overview of the design methodology along with the numerous tools we constructed for evaluation and validation. These tools include (1) simulators to evaluate instruction set trade-offs and microarchitecture features, (2) simulators for performance validation of the hardware, (3) simulators for multiprocessor, system-level, and alternative architecture evaluation, and (4) software development tools customized to the TRIPS architecture.  I will also talk about our validation methodology, which was made viable by the hierarchical nature of the design; to date, we have found no logic design bugs in the chip.  However, our experience showed that finding performance bugs was much more difficult than finding correctness bugs.  Finally, I will outline some modeling challenges for the development of future complex systems.


Biography: Stephen W. Keckler is an Associate Professor of Computer Sciences and Electrical and Computer Engineering at UT-Austin.  His research interests include computer architecture, parallel and embedded processors, VLSI design, adaptive computing, and the influence of technology trends on computer system design.  With Doug Burger, he co-leads the TRIPS project which has developed and prototyped high performance adaptive computer systems.  Dr. Keckler has received an NSF CAREER award, multiple IBM Faculty Fellowship awards, and the 2003 ACM Grace Murray Hopper award; he is also an Alfred P. Sloan Foundation Research Fellow.  He holds a BS in electrical engineering from Stanford University and an MS and a PhD in computer science from the Massachusetts Institute of Technology.



Session 1: Modeling and Simulation (2:00pm to 3:00pm)


An Improved Analytical Superscalar Microprocessor Memory Model [Slides]

Xi E. Chen and Tor M. Aamodt (University of British Columbia)


MIDAS: An Execution-Driven Simulator for Active Storage Architectures [Slides]

Shahrukh Rohinton Tarapore (Lockheed Martin Advanced Technology Labs), Clinton Wills Smullen, IV (University of Virginia), and Sudhanva Gurumurthi (University of Virginia)



Break (3:00pm to 3:30pm)



Session 2: Parallel Simulation and Methodology (3:30pm to 5:30pm)

Chair: TBA


CMP$im: A Pin-Based On-the-Fly Single/Multi-core Cache Simulator

Aamer Jaleel (Intel Corporation, VSSAD), Robert S. Cohn (Intel Corporation, VSSAD), Chi-Keung Luk (Intel Corporation, VSSAD), Bruce Jacob (University of Maryland, College Park)


Runtime variability in scientific parallel applications [Slides]

Wim Heirman, Joni Dambre, Dirk Stroobandt, and Jan Van Campenhout (Ghent University)


Fast Functional Simulation with Parallel Embra [Slides]

Robert E. Lantz (Stanford University)


An Integrated Performance Estimation Approach in a Hybrid Simulation Framework [Slides]

Lei Gao, Stefan Kraemer, Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, and Heinrich Meyr (Aachen University)




Closing Remarks (5:30pm to 5:35pm)

Organizers:     Lieven Eeckhout (Ghent University)

                        Joshua J. Yi (Freescale Semiconductor)