Joshua J. Yi

I received my Ph.D. degree in Electrical Engineering from the University of Minnesota in December 2003. My advisor was Professor David J. Lilja. The focus of my Ph.D. thesis was microarchitecture and statistically-based simulation methodology and analysis.

Between 2004 and 2009, I worked at Freescale Semiconductor (formerly Motorola's semiconductor division, now part of NXP) designing microprocessors and doing performance analysis.

I got my law degree from University of Texas School of Law in 2012.

Between 2012 and 2019, I worked at Dechert LLP as patent litigator, where I was part of three trial teams that obtained jury verdicts in Marshall, TX. (We went 2-1.)

I am currently working as a term law clerk on all patent cases for the Honorable Alan D Albright in the Waco division of the Western District of Texas.

Education

• J.D., 2012, University of Texas at Austin
• Ph.D., Electrical Engineering, 2003, University of Minnesota--Twin Cities
• M.S., Electrical Engineering, 1999, University of Minnesota--Twin Cities
• B.S., Electrical Engineering, 1996, University of Minnesota--Twin Cities

Publications - Please respect the copyrights
(My philosophy when writing papers)

• Joshua J. Yi, "Improving Processor Performance and Simulation Methodology," University of Minnesota, 2003.

• David J. Lilja and Joshua J. Yi, "Statistical Tools for Computer Performance Analysis," Chapter 5 in Performance Evaluation and Benchmarking, edited by Lizy Kurian John and Lieven Eeckhout, CRC Press, ISBN: 0849336228.
  
• Joshua J. Yi, Resit Sendag, and David J. Lilja, "Instruction Precomputation: Dynamically Removing Redundant Computations Using Profiling," Chapter 10 in Speculative Execution in Modern Computer Architectures, edited by Pen-Chung Yew and David Kaeli, CRC Press, ISBN 1-58488-447-9.
• Joshua J. Yi and David J. Lilja, "Computer Architecture," Chapter 9 in Handbook of Nature-Inspired and Innovative Computing: Integrating Classical Models with Emerging Technologies, edited by Albert Zomaya, Springer-Verlag, ISBN: 0-387-40532-1.

• Mustafa Cavus, Resit Sendag, and Joshua J. Yi, "Informed Prefetching for Indirect Memory Accesses," ACM Transactions on Architecture and Optimization, Vol. 17, No. 1, March 2020, pp. 1-29.
• Babak Falsafi, Bill Dally, Desh Singh, Derek Chiou, Joshua J. Yi, and Resit Sendag, "FPGAs versus GPUs in Data centers," IEEE Micro, Vol. 37, No. 1, 2017, pp. 60-72.
• Mark D. Hill, Dave Christie, David Patterson, Joshua J. Yi, Derek Chiou, and Resit Sendag, "Proprietary versus Open Instruction Sets," IEEE Micro, Vol. 36, No. 4, 2016, pp. 56-68.
• Trevor Mudge, Frederic T. Chong, Igor L. Markov, Resit Sendag, Joshua J. Yi, and Derek Chiou, "Impact of Future Technologies on Architecture," IEEE Micro, Vol. 36, No. 4, 2016, pp. 48-56.
• James Hoe, Doug Burger, Joel Emer, Derek Chiou, Resit Sendag, and Joshua J. Yi, "The Future of Architectural Simulation," IEEE Micro, Vol. 30, No. 3, May/June 2010, pp. 8-18.
• Arvind, David August, Keshav Pingali, Derek Chiou, Resit Sendag, and Joshua J. Yi, "Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?," IEEE Micro, Vol. 30, No. 3, May/June 2010, pp. 19-33.
• Resit Sendag, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, "The Impact of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems," Journal of Parallel and Distributed Computing, Special Issue on Best Papers in International Parallel and Distributed Processing Symposium, Vol. 67, No. 12, pp. 1256-1269, December 2007.
• Joel Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, and Resit Sendag, "Single-Threaded vs. Multithreaded: Where Should We Focus?," IEEE Micro, Vol. 27, No. 6, November/December 2007, pp. 14-24.
• Shay Gueron, Jean-Pierre Seifert, Geoffrey Strongin, Derek Chiou, Resit Sendag, and Joshua J. Yi, "Where Does Security Stand? New Vulnerabilities vs. Trusted Computing," IEEE Micro, Vol. 27, No. 6, November/December 2007, pp. 25-35.
• Antonio González, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, and Joshua J. Yi, "Reliability: Fallacy or Reality?," IEEE Micro, Vol. 27, No. 6, November/December 2007, pp. 36-45.
• Kevin Skadron, Pradip Bose, Kanad Ghose, Resit Sendag, Joshua J. Yi, and Derek Chiou, "Low-Power Design and Temperature Management," IEEE Micro, Vol. 27, No. 6, November/December 2007, pp. 46-57.
• Joshua J. Yi, Resit Sendag, David J. Lilja, and Douglas M. Hawkins "Speed and Accuracy Trade-offs in Microarchitectural Simulations," IEEE Transactions on Computers, Vol. 56, No. 11, November 2007, pp. 1549-1563.
• Resit Sendag, Joshua J. Yi, and Peng-fei Chuang "Branch Misprediction Prediction: Complementary Branch Predictors," IEEE Computer Architecture Letters, Vol. 6, September 2007.
• Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy K. John, and James E. Smith, "The Future of Simulation: A Field of Dreams?," IEEE Computer, Vol. 39, No. 11, November 2006, pp. 22-29.
• Joshua J. Yi and David J. Lilja, "Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations," IEEE Transactions on Computers, Vol. 55, No. 3, March 2006, pp. 268-280.
• Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins, "Improving Computer Architecture Simulation Methodology by Adding Statistical Rigor," IEEE Transactions on Computers, Vol. 54, No. 11, November 2005, pp. 1360-1373.

• Mustafa Cavus, Resit Sendag, and Joshua J. Yi, "Array Tracking Prefetcher for Indirect Accesses." International Conference on Computer Design, October 2018. Acceptance Rate: Unknown
• Resit Sendag, Joshua J. Yi, Peng-fei Chuang, and David Lilja, "Low Power/Area Branch Prediction Using Complementary Branch Predictors," International Parallel and Distributed Processing Symposium, April 2008. Acceptance Rate: 26%
• Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, and Lizy K. John, "Evaluating Benchmark Subsetting Approaches," International Symposium on Workload Characterization, October 2006. Acceptance Rate: 30%
• Joshua J. Yi, Hans Vandierendonck, Lieven Eeckhout, and David J. Lilja, "The Exigency of Benchmark and Compiler Drift: Designing Tomorrow's Processors With Yesterday's Tools," International Conference on Supercomputing, June 2006. Acceptance Rate: 26%
• Resit Sendag, Ayse Yilmazer, Joshua J. Yi, and Augustus K. Uht, "Quantifying and Reducing the Effects of Wrong-Path Memory References in Cache-Coherent Multiprocessor Systems," International Parallel and Distributed Processing Symposium, April 2006. Acceptance Rate: 24%.
  Best Paper Award Winner!
• Ajay Joshi, Joshua J. Yi, Robert H. Bell Jr., Lieven Eeckhout, Lizy K. John, and David J. Lilja, "Evaluating the Efficacy of Statistical Simulation for Design Space Exploration," International Symposium on Performance Analysis of Systems and Software, March 2006. Acceptance Rate: 30%
  
• Lieven Eeckhout, Rashmi Sundareswara, Joshua J. Yi, David J. Lilja, and Paul Schrater, "Accurate Statistical Approaches for Generating Representative Workload Compositions," International Symposium on Workload Characterization, October 2005. Acceptance Rate: 33%. Errata
• Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, and Douglas M. Hawkins, "Characterizing and Comparing Prevailing Simulation Techniques," International Symposium on High-Performance Computer Architecture, February 2005. Acceptance Rate: 15%.
• Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins, "A Statistically Rigorous Approach for Improving Simulation Methodology," International Symposium on High-Performance Computer Architecture, February 2003. Acceptance Rate: 22%.
• Joshua J. Yi and David J. Lilja, "Improving Processor Performance by Simplifying and Bypassing Trivial Computations," International Conference on Computer Design, September 2002. Acceptance Rate: 39%.
• Joshua J. Yi, Resit Sendag, and David J. Lilja, "Increasing Instruction-Level Parallelism with Instruction Precomputation," Euro-Par, August 2002. Acceptance Rate: 46%.

• Ayse Yilmazer, Resit Sendag, and Joshua J. Yi, "Quantifying and Comparing the Impact of Wrong-Path Memory References in Multiple-CMP Systems," Workshop on Chip Multiprocessor Memory Systems and Interconnects, February 2007. Acceptance Rate: Unknown.
• Resit Sendag, Joshua J. Yi, and Peng-fei Chuang, "Predicting When a Branch Predictor Will Fail," Boston Area Architecture Workshop, January 2007. Acceptance Rate: Unknown.
• Ayse Yilmazer, Resit Sendag, Joshua J. Yi, and Augustus K. Uht, "Investigating the Effects of Wrong-Path Memory References in Shared-Memory Multiprocessor Systems," Boston Area Architecture Workshop, February 2006. Acceptance Rate: Unknown.
• Joshua J. Yi, Ajay Joshi, Resit Sendag, Lieven Eeckhout, and David J. Lilja, "Analyzing the Processor Bottlenecks in SPEC CPU 2000," SPEC Benchmark Workshop, January 2006. Acceptance Rate: Unknown.
  Kaivalya Dixit Award for the Best Paper!
• Joshua J. Yi and David J. Lilja, "An Analysis of the Amount of Global Level Redundant Computation in the SPEC 95 and SPEC 2000 Benchmarks," Workshop on Workload Characterization, December 2001. Acceptance Rate: 54%.

• Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, and Douglas M. Hawkins, "Characterizing and Comparing Prevailing Simulation Techniques," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 04-06, November 2004.
• Joshua J. Yi, Resit Sendag, and David J. Lilja, "The Spatial Characteristics of Load Instructions," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 02-10, October 2002.
• Joshua J. Yi, David J. Lilja, and Douglas M. Hawkins, "A Statistically Rigorous Approach for Improving Simulation Methodology," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 02-07, September 2002.
• Joshua J. Yi and David J. Lilja, "Improving Processor Performance by Simplifying and Bypassing Trivial Computations," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 02-06, June 2002.
• Joshua J. Yi and David J. Lilja, ""Effects of Processor Parameter Selection on Simulation Results," Minnesota Supercomputer Institute Report 2002/146, 2002.
• Joshua J. Yi, Resit Sendag and David J. Lilja, "Increasing Instruction-Level Parallelism with Instruction Precomputation," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 02-01, February 2002.
• Joshua J. Yi and David J. Lilja, "An Analysis of the Potential for Global Level Value Reuse in the SPEC 95 and SPEC 2000 Benchmarks," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 01-01, May 2001.
• Youngsoo Choi, Joshua J. Yi, Jian Huang, and David J. Lilja, "Improving Value Prediction by Exploiting Both Operand and Output Value Locality," Laboratory for Advanced Research in Computing Technology and Compilers Technical Report ARCTiC 00-09, July 2000.

Professional Activities

• Co-Organizer (with Derek Chiou and Resit Sendag) of the Fifth Workshop on Computer Architecture Research Directions (CARD),
  Held in conjunction with the International Symposium on Computer Architecture, June 2019.
• Co-Organizer (with Derek Chiou and Resit Sendag) of the Fourth Workshop on Computer Architecture Research Directions (CARD),
  Held in conjunction with the International Symposium on Computer Architecture, June 2015.
• Co-Organizer (with Derek Chiou and Resit Sendag) of the Third Workshop on Computer Architecture Research Directions (CARD),
  Held in conjunction with the International Symposium on Computer Architecture, June 2011.
• Workshop/Tutorial Chair for IEEE International Symposium on Workload Characterization (IISWC), October 2009.
• Co-Organizer and Co-Chair (with Lieven Eeckhout and Thomas Wenisch) of the Fifth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS),
  Held in conjunction with the International Symposium on Computer Architecture, June 2009.
• Co-Organizer (with Derek Chiou and Resit Sendag) of the Second Workshop on Computer Architecture Research Directions (CARD),
  Held in conjunction with the International Symposium on Computer Architecture, June 2009.
• Co-Organizer and Co-Chair (with Lieven Eeckhout) of the Fourth Annual Workshop on Modeling, Benchmarking and Simulation (MoBS),
  Held in conjunction with the International Symposium on Computer Architecture, June 2008.
• Program committee member of the 2007 IEEE Internaional Symposium on Workload Characterization (IISWC), September 2007.
• Co-Organizer and Co-Chair (with Lieven Eeckhout) of the Third Annual Workshop on Modeling, Benchmarking and Simulation (MoBS),
  Held in conjunction with the International Symposium on Computer Architecture, June 2007.
• Co-Organizer (with Derek Chiou and Resit Sendag) of the First Workshop on Computer Architecture Research Directions (CARD),
  Held in conjunction with the International Symposium on High-Performance Computer Architecture, February 2007.
• Co-Guest Editor (with Tim Sherwood) of the IEEE Micro Special Issue on Simulation and Modeling , IEEE Micro, Vol. 26, No. 4., July/August 2006.
  
• Co-Organizer and Co-Chair (with Lieven Eeckhout) of the Second Annual Workshop on Modeling, Benchmarking and Simulation (MoBS),
  Held in conjunction with the International Symposium on Computer Architecture, June 2006.
• Registration Chair for IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2006.
• Registration Chair for IEEE International Symposium on Workload Characterization (IISWC), October 2005.
• Co-Organizer and Co-Chair (with Lieven Eeckhout) of the First Annual Workshop on Modeling, Benchmarking and Simulation (MoBS),
  Held in conjunction with the International Symposium on Computer Architecture, June 2005.
• Co-Organizer and Co-Moderator (with David J. Lilja) of the Panel: "The Future of Simulation: A Field of Dreams?",
  International Symposium on Performance Analysis of Systems and Software, March 2004.

Research Interests (In Alphabetical Order)

• Low Power Design
• Design Methodology and Optimization
• Experimental Computer Architecture Methodology
• Multi-core SoC design
• Processor reliability
• Superscalar Processor Design

Contact Information